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ADT7490
THERM
timer value exceeds the THERM timer limit value, the
FAN4 bit (Bit 5) of Status Register 2 is set and an
SMBALERT is generated.
THERM
TIMER
(REG. 0x79)
0 0 0 0 0 0 0 1
7 6 5 4 3 2 1 0
THERM ASSERTED
? 22.76 ms
Note that depending on which pins are configured as a
THERM timer, setting the FAN4/THERM bit (Bit 5) of the
Interrupt Mask Register 2 (0x75), o r bit 0 of th e Interrupt
Mask Register 1 (0x74), masks out SMBALERT; although
THERM
ACCUMULATE THERM LOW
ASSERTION TIMES
the FAN4 bit of Interrupt Status Register 2 is still set if the
THERM timer limit is exceeded.
Figure 34 is a functional block diagram of the THERM
timer, THERM limit, and its associated circuitry. Writing a
value of 0x00 to the THERM Timer Limit register (0x7A)
THERM
TIMER
(REG. 0x79)
THERM
0 0 0 0 0 0 1 0
7 6 5 4 3 2 1 0
THERM ASSERTED
? 45.52 ms
causes an SMBALERT to be generated on the first THERM
assertion. A THERM timer limit value of 0x01 generates an
SMBALERT once cumulative THERM assertions exceed
45.52 ms.
Configuring the Relevant THERM Behavior
1. Configure the desired pin as the THERM timer
input. Setting Bit 1 (THERM timer enable) of
ACCUMULATE THERM LOW
ASSERTION TIMES
Configuration Register 3 (Register 0x78) enables
the THERM timer monitoring functionality. This is
disabled on Pin 14 and Pin 22 by default.
THERM
TIMER
(REG. 0x79)
0 0 0 0 0 1 0 1
7 6 5 4 3 2 1 0
THERM ASSERTED
? 113.8 ms
(91.04 ms + 22.76 ms)
Setting Bit 0 and Bit 1 (Pin 14 Func) of
Configuration Register 4 (Register 0x7D) enables
THERM timer output functionality on Pin 22 (Bit 1
of Configuration Register 3, THERM, must also be
Figure 33. Understanding the THERM Timer
When using the THERM timer, be aware of the following:
After a THERM timer read (Register 0x79):
? The contents of the timer are cleared on read.
? Bit 5 of Interrupt Status 2 register (0x42) needs to be
cleared (assuming that the THERM timer limit has
been exceeded).
If the THERM timer is read during a THERM assertion,
the following happens:
? The contents of the timer are cleared.
? Bit 0 of the THERM timer is set to 1, because a
THERM assertion is occurring.
? The THERM timer increments from zero.
? If the THERM timer limit (Register 0x7A) = 0x00, the
F4P bit is set.
Generating SMBALERT Interrupts from THERM Timer
Events
The ADT7490 can generate SMBALERTs when a
programmable THERM timer limit has been exceeded. This
allows the system designer to ignore brief, infrequent
THERM assertions while capturing longer THERM timer
events. Register 0x7A is the THERM timer limit register.
This 8-bit register allows a limit from 0 sec (first THERM
assertion) to 5.825 sec to be set before an SMBALERT is
generated. The THER M timer value is compared with the
contents of the THERM timer limit register. If the THERM
set). Pin 14 can also be used as TACH4.
2. Select the desired fan behavior for THERM timer
events. Assuming the fans are running, setting Bit 2
(BOOST bit) of Configuration Register 3
(Register 0x78) causes al l fans to run at 100% duty
cycle whenever THERM is asserted.
This allows fail-safe system cooling. If this bit = 0,
the fans run at their current settings and are not
affected by THERM events. If the fans are not
already running when THERM is asserted, the fans
do not run to full speed.
3. Select whether THERM timer events should
generate SMBALERT interrupts.
Bit 5 of Interrupt Mask Register 2 (0x75) or Bit 0
of Interrupt Mask Register 1 (0x74), depending on
which pins are configured as a THERM timer,
when set , masks out SMBALERTs when the
THERM timer limit value is exceeded. This bit
should be cleared if SMBALERTs based on
THERM events are required.
4. Select a suitable THERM limit value.
This value determines whether an SMBALERT is
generated on the first THERM assertion, or only if
a cumulative THERM assertion time limit is
exceeded. A value of 0x00 causes a n SMBALERT
to be generated on the first THERM assertion.
5. Select a THERM monitoring time.
This value specifies how often OS- or BIOS-level
software checks the THERM timer. For example,
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